Chiplet IP

Chiplet IP

We explore next-generation advanced packaging technologies and architectures. The advanced W2W or C2W hybrid bonding will be one of the key technologies to enable future high level 3D system integration such as memory on logic or verse versa, logic on logic. Here thermal challenges due to the Joule heating impact and IR drop will be exacerbated. Therefore, power integrity (PI), signal integrity (SI), and thermal-stress integrity all need to be well managed. Different packaging format will also be evaluated such as CoWoS, CoPoS and CoWoP in order to provide our customer the satisfied COO. 

UCIe & 3D UCIe

•UCIe & 3D UCIe

3D thermal-stress modeling

•3D thermal-stress modeling